1. Field of the Invention
The invention relates to a protection device. Particularly, the invention relates to an electrostatic discharge (ESD) protection device.
2. Description of Related Art
Electrostatic discharge (ESD) is usually a main reason to cause electrostatic overstress of an integrated circuit (IC) or permanent damage thereof, and a commonly-used method is to add an ESD protection device between a core circuit and a pad to prevent ESD damage. In various ESD protection devices, a diode-triggered silicon controlled rectifier (DTSCR) is widely applied in various types of ICs due to its characteristics of low trigger voltage and fast turn-on speed.
FIG. 1 is cross-sectional view of a conventional DTSCR. Referring to FIG. 1, the DTSCR 100 includes a P-type substrate 110 and a P-type well region 120 and N-type well regions 131-134 configured in the P-type substrate 110. Moreover, P+-type doped regions 141-145 and N+-type doped regions 151-155 are alternately configured in the P-type well region 120 and the N-type well regions 131-134. In view of electrical connection, a plurality of diodes formed by the P+-type doped regions 142-145 and the N-type well regions 131-134 are connected in series between a pad 101 and a ground wire GND1. Moreover, the P+-type doped region 141 and the N+-type doped region 151 in the P-type well region 120 and a P+-type doped region 146 in the P-type substrate 110 are all electrically connected to the ground wire GND1.
In this way, a layout structure of the DTSCR 100 is equivalent to a circuit diagram shown in FIG. 2. As shown in FIG. 2, the DTSCR 100 includes a silicon controlled rectifier circuit composed of a PNP transistor MP21 and an NPN transistor MN2, PNP transistors MP22-MP24 connected in Darlington configuration and a resistor R2. In operation, ESD events can be classified in to several modes, for example, PS mode and NS mode. Wherein, the PS mode is the case when a positive pulse signal is applied for the pad 101 with the ground wire GND1 is grounded, and the NS mode is the case when a negative pulse signal is applied for the pad 101 with the ground wire GND1 is grounded. When an electrostatic signal from the pad 101 is a positive pulse signal, i.e. when a PS mode ESD event occurs, the PNP transistors MP22-MP24 contribute a tiny current to trigger the silicon controlled rectifier circuit composed of the PNP transistor MP21 and the NPN transistor MN2. In this way, the positive pulse signal from the pad 101 can be guided to the ground wire GND1 through the silicon controlled rectifier circuit.
However, when the electrostatic signal from the pad 101 is a negative pulse signal, i.e. when an NS mode ESD event occurs, the DTSCR 100 cannot provide a discharge path. In other words, the DTSCR 100 does not have an NS mode ESD protection function, so that the IC has to be additionally configured with an inverse diode D2. Moreover, when a core circuit 102 normally operates, the diode string formed by the N-type well regions 131-134 and the P+-type doped regions 142-145 is biased under a forward bias. Now, the equivalent PNP transistors MP22-MP24 in the DTSCR 100 produce a vertical leakage path, which may cause a large leakage current of the DTSCR 100.
In other words, the DTSCR 100 cannot satisfy a condition of low leakage current required by a high-speed transmission device, so that it cannot be applied in the high-speed transmission device. Moreover, the DTSCR 100 does not have the NS mode ESD protection function.